IBM has unveiled a new semiconductor technology, claiming it is the world's first capable of producing transistors with dimensions of less than one nanometer. This move aims to increase chip density and improve performance and efficiency in response to the growing demand for computing power required by artificial intelligence.

The technology is based on a 0.7-nanometer (7-angstrom) transistor architecture, which the company has dubbed "NanoStack." Instead of simply distributing transistors horizontally, the new architecture allows them to be stacked vertically in three dimensions, enabling a greater number of them to fit within the same space.

According to IBM, the new technology can pack approximately 100 billion transistors onto a chip roughly the size of a fingernail. This is roughly double the density achieved by the company's 2-nanometer technology, which it announced in 2021. The

company expects the new architecture to deliver up to a 50 percent performance increase or a 70 percent improvement in power efficiency compared to its previous 2-nanometer generation. The choice between higher performance and lower power consumption depends on the chip's design and application requirements.

These figures are particularly important with the increasing use of generative AI models, which require massive processing power and consume significant amounts of electricity in data centers. Increasing the number of transistors allows for more operations to be performed in a smaller space, potentially reducing power consumption or improving speed. Overcoming

the limitations of miniaturization:

In recent years, the chip industry has faced increasing difficulty in continuing to miniaturize transistors using traditional methods. As their dimensions approach the atomic level, increasing density becomes more complex, and problems related to power leakage, heat, and manufacturing precision emerge.

The NanoStack architecture attempts to address these limitations by exploiting the vertical dimension. Instead of relying solely on miniaturizing components and placing them side-by-side, they are stacked on top of each other, increasing the number of components that can be integrated within the same volume.

Jay Gambetta, director of IBM Research, said the new architecture focuses not only on making smaller transistors but also on redesigning how chips are built to achieve greater increases in computing power and energy efficiency.